This invention relates to the generation, compression and decompression of stimulus waveforms and the capture, compression and decompression of response waveforms in automated test and measurement systems, especially systems that accept and/or generate electrical and/or optical signals.
In commonly owned U.S. Pat. No. 7,071,852 B1 (“the '852 patent”), entitled “Enhanced Test and Measurement Instruments Using Compression and Decompression,” dated Jul. 4, 2006 and herein incorporated by reference, the present inventor discloses compression and decompression methods for test and measurement instruments, including arbitrary waveform generators (AWG) and digital storage oscilloscopes (DSO). In the commonly owned and copending U.S. patent application, application Ser. No. 11/458,771 (the '771 application) entitled, “Enhanced Time-Interleaved A/D Conversion Using Compression,” filed on Jul. 20, 2006 and herein incorporated by reference, the present inventor describes compression of a bandlimited signal that is sampled by a parallel time-interleaved analog-to-digital converter (TIADC). The compression methods described therein are designed to take advantage of the parallel architecture of the TIADC. The compression methods of the '771 application can be implemented in a test and measurement system that includes a TIADC. In the commonly owned and copending U.S. patent application, Ser. No. 11/553,147 (the '147 application), entitled “Data Compression for a Waveform Data Analyzer”, filed on 26 Oct. 2006 and herein incorporated by reference, the present inventor describes compression of waveform having recurring waveform states and teaches algorithms for this particular type of waveform.
It is a well known practice in the art to test electronic devices by applying a digital or an analog stimulus to the input of a system under test (SUT), device under test (DUT) or a circuit under test (CUT) and to analyze the response to determine proper operation. Using this methodology, automatic test equipment (ATE) systems test billions of integrated circuits (ICs), or “chips,” each year, including mixed-signal and system-on-chip (SoC) devices. The stimulus and response methodology is used to test individual integrated circuits, printed circuit boards, systems, electronic products and the like. Regardless of the item being tested, the methodology of applying a stimulus to a SUT, DUT or CUT and observing the response is common practice in the test and measurement field. Depending on the system or device being tested, the stimulus and response signals can be electrical or optical. Because of the common stimulus and response methodology, the terms SUT, DUT and CUT are used interchangeably in the following discussion and are not intended to limit the scope to testing any particular circuit, device or system.
A desirable goal of automated test systems is to test a SUT as quickly as possible. Mixed-signal devices and SoC devices are increasingly used in high-volume, low-cost consumer electronics, such as in mobile phones, digital cameras and digital music players. As the prevalence of mixed-signal and SoC devices increases, so does the importance of testing these devices in an efficient, cost-effective manner.
Many SUTs have an analog input or an analog output. Testing these SUTs can require converting digital waveform samples to a corresponding analog stimulus waveform prior to stimulating the device or converting an analog response waveform from the device to a corresponding digital form. For this reason, many ATE systems include analog-to-digital converters (ADC) and digital-to-analog converters (DAC).
In many ATE systems, both stimulus and response signals are created, stored and manipulated in digital form. Stimulus signals are often stored in digital form in at least one stimulus memory. Storing stimulus waveforms provides flexibility to the testing process because the stimulus waveform can easily be created, retrieved, copied, moved, repeated, or reordered before being applied to the SUT. Similarly, response waveforms are often captured in digital form in at least one capture memory. When response waveforms are captured in digital form, they can easily be retrieved, measured, copied and transferred from one ATE subsystem to another.
It is common practice to implement stimulus and response memories using dynamic random access memory (DRAM) integrated circuits or DRAM modules, or using static random access memory (SRAM), or using flash memory (NOR or NAND flash). Stimulus and response memories can also be implemented using rotating media such as magnetic disk drives, CD-ROM drives, optical drives, DVD drives, and the like. The memory described herein applies to any form of data storage and is not limited to any particular physical implementation.
Stimulus and response memories can create bottlenecks in an ATE system because they have both limited capacity and limited access bandwidth. In particular, stimulus memory becomes a bottleneck when it cannot store all stimulus waveforms for a particular test or it cannot be accessed fast enough to accommodate the input data rate of the SUT. Similarly, response memory becomes a bottleneck when its access rate is too slow or its capacity is insufficient to capture the response waveform data from the SUT.
Other bottlenecks can arise as a result of the architecture of the ATE system. In many ATE systems the SUT is attached to one part of the test system called the “test head” and the overall control of the ATE system is performed by a controlling computer. Often, the controlling computer is the original source of stimulus waveforms and the ultimate destination of response waveforms. The limited bandwidth of the connection between the test head and the SUT limits the data transfer rate, creating an additional bottleneck. In the following discussion, an “instrument” refers to a printed circuit board or card in the test head.
In some ATE systems, the stimulus waveforms are generated by one or more arbitrary waveform generators (AWG) in the test head. An AWG generates an analog stimulus waveform by reading waveform samples from a memory and using a DAC to convert the samples to an analog stimulus waveform. The test head can also include one or more digitizers for capturing an analog response waveform. A digitizer converts the analog response waveform using an ADC and stores the response waveform samples in a memory.
The test head may include other instruments to generate digital stimulus patterns that are applied directly to the serial or parallel inputs of the DUT. For example, when testing a DAC, the ATE provides the digital stimulus waveform, such as DC levels, ramps, sawtooths, sine waves, etc., directly to the serial or parallel inputs of the DAC. The analog output of the DAC under test is captured by a digitizer and sampled as described above. Other response capture instruments in the test head can capture digital response waveforms directly from the DUT. For example, when testing an ADC, the ATE provides an analog stimulus waveform to the ADC. The ADC samples the analog stimulus waveform to provide digital response waveform samples on its serial or parallel outputs. The ATE response capture instrument stores the samples in a capture memory.
Emerging technologies in the field of IC test and measurement include built-in self test (BIST), design-for-manufacturability (DFM) and design-for-test (DFT). These emerging technologies address the problems of testing ICs with increasing complexity and on-chip clock rates substantially higher than chip interface rates by including stimulus generators and response capture circuitry within the IC itself. In BIST architectures, testing cores are integrated with the system to be tested to mitigate the limitations of the chip interface. The present invention is suitable for integration as an enhancement for stimulus generation, response capture, or both, and thus improves existing BIST, DFM, and DFT practices.
FIG. 1 is a block diagram showing an example of a typical test system from the prior art. A SUT 200 is stimulated with an analog stimulus waveform 190 or a digital stimulus waveform 160. The SUT 200 produces an analog response 220 and/or a digital response 210 that are captured for further processing. The host processor 100 coordinates the various operations required to perform the test. The host processor 100 can have any architecture appropriate for the test system, including mainframe, personal computer (PC), card-based and embedded. The host processor 100 provides at least one stimulus waveform to a stimulus memory 150 via a stimulus memory interface 120. When the test requires a digital stimulus, digital stimulus waveform 160 is retrieved from the stimulus memory 150 and provided to the digital input of SUT 200. When the test requires an analog stimulus, stimulus waveform samples retrieved from stimulus memory 150 are provided to the DAC 180 via DAC input 170. The DAC 180 converts the stimulus waveform samples into the analog stimulus waveform 190 at a given sample rate. The analog stimulus waveform 190 is applied to the analog input of SUT 200. A digital response waveform 210 output from the SUT 200 is captured in a response memory 250. An analog response waveform 220 from the SUT 200 is first digitized by the ADC 230 to produce a sampled response waveform 240 whose samples are stored in response memory 250. The samples in response memory 250 can be retrieved by host processor 100 via a response memory interface 270. The host processor 100 then performs further analysis, measurements, calculations, statistics-gathering and display operations.
FIG. 2 illustrates an example of a configuration for an ATE system from the prior art. Host processor 100, in this case a mainframe computer, is attached to test head 300 via a mainframe to test head interface 315. Mainframe to test head interface 315 can be implemented by a variety of technologies using electrical or optical cables, Ethernet (10/100/1000/10G-baseT variants) networks, USB cables, other parallel or serial cables, or busses such as PCI, PCI Express (PCIe), VME, VXI, PXI, etc. Test head 300 includes stimulus memory 150 and response memory 250. As described with respect to of FIG. 1, stimulus memory 150 provides digital stimulus waveform samples that are applied in a controlled sequence to the digital input of DUT 200. Alternatively, stimulus waveform samples from stimulus memory can be converted to an analog stimulus waveform by a DAC (not shown in FIG. 2) that is applied to the analog input of DUT 200. Similarly, response memory 250 stores the digital response waveform or a digitized version of the analog response waveform from DUT 200. Examples of commercially available ATE testers with this architecture include the Advantest T7611 and the Credence Sapphire D-40.
FIG. 3 is a block diagram of another configuration of a test system from the prior art. Host processor 100, in this case a personal computer, communicates with test chassis 330 using chassis interface 320. Test chassis 330 contains stimulus memory 150, whose output is used to stimulate the digital and/or analog inputs of SUT 200 via SUT interface 340. Similarly, the digital and/or analog outputs of SUT 200 are captured in response memory 250 via SUT interface 340. Examples of commercially available PC-based test systems include products from National Instruments. The National Instruments PXI test system includes multiple PXI (PCI eXtensions for Instrumentation) cards in a test chassis. The PC is implemented as a PXI card in the test chassis. The test chassis also contains a second PXI card that includes stimulus memory and a third PXI card that includes response memory. All PXI cards in test chassis can communicate using the chassis interface, also called a bus, interconnect, or backplane. National Instruments also offers a product where the test chassis is an instrumentation peripheral that uses the popular Universal Serial Bus (USB) to communicate with a laptop PC. In National Instruments compactDAQ™ product, the test chassis contains up to eight removable cards. One of the compactDAQ cards includes stimulus memory and a second compactDAQ card includes response memory. The test chassis communicates with the PC using a USB for the chassis interface. The compactDAQ card containing stimulus memory and the compactDAQ card containing response memory communicate with the SUT.
The prior art systems of FIGS. 1, 2 and 3 have the following limitations that reduce testing efficiency:                Stimulus memory interfaces 120, 160 and 170 have limited bandwidths,        Response memory interfaces 270, 210 and 240 have limited bandwidths,        Mainframe to test head interface 315 and chassis interface 320 have limited bandwidths,        Stimulus memory 150 and response memory 250 have limited storage capacities,        Delays are incurred when host processor 100 transfers stimulus waveforms to stimulus memory 150 over interface 315 or 320 with limited bandwidths,        Delays are incurred when host processor 100 retrieves the response waveform samples via interface 315 or 320 from response memory 250 prior to analysis.        
The above limitations can be mitigated by compression and decompression to the stimulus waveforms and response waveforms in accordance with the present invention.
Faster testing enabled by the present invention can provide substantial cost savings in the production of ICs. The average cost per hour of testing by an ATE is $100 per hour. The cost savings can be economically significant for the nearly $250 billion worth of ICs sold annually. The cost of testing accounts for between 5% and 10%, conservatively, of the cost of silicon. An estimate of the cost of goods sold, including testing costs, is $100 billion, assuming a 60% gross margin. Based on this estimate, between $5 billion and $10 billion is expended for testing ICs annually. Reducing testing costs by 10% to 20% produces cost savings to the IC industry of $500 million to $2 billion.
The following example of IC testing illustrates how compression of the stimulus and response waveforms prior to transfer over a 1-gigabit Ethernet connection reduces testing time. In this example, a hypothetical mixed-signal IC test system requires a digital stimulus waveform and produces an analog response waveform. The stimulus waveform has 1 million samples, a sample rate of 1 gigasamples/sec. (Gsamp/sec.) and 8 bits per sample. Assume that the IC under test is stimulated for 1 msec., corresponding to the number of samples divided by the sample rate. The response waveform is captured for 1 msec. and digitized at a sample rate of 1 Gsamps./sec. to produce 1 million response waveform samples. Assume that applying compression described in the '147 application (also described below with respect to a preferred embodiment) to the stimulus and response waveform samples results in 2:1 lossless compression. The test system is an example of the architecture of FIG. 2, including a test head and a mainframe connected by a 1-gigabit Ethernet link. Data are exchanged between the test head and main frame at a rate of 125 megabytes/sec, or 125 megasamples/sec, via the Ethernet link. Four steps required to test the DUT are as follows:                1) Load the AWG in the test head with 1 million samples,        2) Generate the stimulus and capture the response in the test head for 1 msec.,        3) Transfer the response samples from the test head to the mainframe, and        4) Perform measurements in the mainframe.        
The following table summarizes the testing times both with and without compression for the above steps:
Test Time withoutTest Time withTest StepCompressionCompressonLoad AWG memory in test head8 msec.4 msec.Run test and capture response in1 msec.1 msec.digitizer memory in test headTransfer response from test head to8 msec.4 msec.mainframeMake measurements in mainframe8 msec.8 msec.TOTAL25 msec. 17 msec. 
The above table shows that total test time is reduced from 25 msec. to 17 msec., for a 30% reduction. For the average cost of testing by an ATE system of $100 per hour, 30% reduction in test time results in a savings of $30 per hour for this particular example.
Other related art for test systems describes compression and decompression of digital scan chains or scan vectors with an emphasis on detecting defects in components of a device. Scan chains and scan vectors can be generated using automatic test pattern generation (ATPG), which takes as input an IC netlist and generates a fault list. The related art does not address the use of compression and decompression in conjunction with stimulus waveforms and captured response waveforms, each having analog or digital forms. Examples that address compression of scan chains and scan vectors are described below. A significant distinction between the present invention's compression and scan chain compression is that scan chains are developed and used as sequences of individual ‘0’ or ‘1’ binary bits, while the present invention processes sequences of groups of N binary bits (not individual ones and zeros), where each N-bit value represents one sample in a sampled data waveform.
In patent U.S. Pat. No. 7,093,174 (the '174 patent) the compaction of scan chain patterns that are used to verify the functionality of individual flip-flops in a digital DUT is described. Scan chains are used to test strings of flip-flops (storage elements) in digital devices for proper operation. Using multiple scan chains, flip-flops and combinatorial logic in each subset of a semiconductor device can be tested. The organization of scan chains in digital devices is usually automatically determined by computer-aided design (CAD) tools. The goal of automated scan chain insertion by CAD tools is to efficiently determine whether flip-flops are operational. There is normally no relation between the functional operation of a DUT and the organization and access patterns of automatically or manually-generated scan chains. The '174 patent does not disclose the compression of digital waveforms that are later decompressed and applied to a DUT, in digital form or in analog form. The '174 patent does not disclose compressing the functional outputs of a DUT, including digital response waveforms or digitized versions of analog response waveforms, prior to storage in a response memory.
U.S. Pat. No. 6,782,501 (the '501 patent) describes compression of digital scan vectors that include long strings of two-valued logic levels, i.e. zeros and ones. The '501 patent cites the presence of “care” and “don't care” bits in the digital scan vectors (stimulus) to be compressed. The scan vectors do not represent digital waveforms that have multiple amplitude values. The '501 patent describes the generation of highly compact “signatures” (16-bit or 32-bit values) from the ones and zeros in the response signal. The “signature” of a response signal is generated through a series of logical and/or arithmetic operations that determine whether the signature of one scan chain is identical to the signature of another scan chain. The “signatures” do not preserve or encode the individual response bits. These “signatures” are used for error detection, just as are cyclic redundancy checks (CRC), error-detecting codes (EDC) and parity codes. The “signatures” do not represent the samples of a digital waveform or analog waveform and cannot be used to reconstruct the entire stream of bits from which the signature was generated. The '501 patent does not disclose reversible compression of stimulus and response waveforms.
In addition to the limitations described above, the related art has additional disadvantages:                the time taken to write uncompressed stimulus waveform samples into a stimulus memory is directly related to the number of uncompressed samples in the stimulus waveform,        the time taken to read uncompressed waveform samples from a response memory is directly related to the number of uncompressed samples in the response waveform,        response capture devices usually do not make measurements, but instead are only capable of capturing waveforms, whose characteristics are later measured by a remote measurement system, such as a computer or ATE mainframe.        